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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 1.1 / dec. 2007 1 256mb synchronous dram base d on 4m x 4bank x16 i/o 256m (16mx16bit) hynix sdram memory memory cell array - organized as 4banks of 4,194,304 x 16
rev 1.1 / dec. 2007 2 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series document title 256mbit (16m x16) synchronous dram revision history revision no. history draft date remark 0.1 initial draft dec. 2005 preliminary 0.2 define : current value (page 11 ~ 12) apr. 2006 preliminary 0.3 1. cerrect : 1-1. 4banks x 2mbits x32 --> 4banks x 4mbits x16 (ordering in- formation; page 05). 1-2. vddq / vssq : power supply for output buffers (page 07). 2. remove : special power consumption functi on of auto tcsr(temperature compensated self refresh) and pasr(partial array self refresh). 43. specification change : 3-1. ioh / iol (page 10) before : -2 / 2ma --> after : -4 / 4ma. 3-2. tdh, tah, tckh, tch (page 12) before : 1.0ns --> after : 0.8ns. 4. specitication change : 4-1. idd6 before : 1.5 / 0.8ma --> after : 2 / 1ma 4-2. idd3n before :25ma --> after : 30ma 4-3. tchw / tclw change [hy57v56(p)-6x] before :2.0ns --> after : 2.5ns jun. 2006 preliminary 1.0 final ver. final final 1.1 1. correct : separate normal power and low power dc characteristics (page 10) dec. 2007 final
rev 1.1 / dec. 2007 3 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series description the hynix synchronous dram is suited for advaced-consumer application which use the batteries such as image dis- player application (digital still camera etc.) and portable applications (portable multimed ia player and portable audio player). also, hynix sdrams is used high-speed consumer applications. short for hynix synchronous dram, a type of dram that can run at much higher clock speeds memory. the hynix hy5v56f(l)f(p) synchronous dram is 268,435,456b it cmos synchronous dram, ideally suited for the con- sumer memory applications wh ich requires large memory density and high bandwidth. it is organized as 4banks of 4,194,304 x 16 i/o. synchronous dram is a type of dram which operates in synchronization with input clock. the hynix synchronous dram latch each control signal at the rising edge of a basi c input clock (clk) and input/ou tput data in synchronization with the input clock (clk). the address lines are multiplexed with the data input/ output signals on a multiplexed x16 input/ output bus. all the commands are latched in synchronization with the rising edge of clk. the synchronous dram provides for programmable read or write burst length of programmable burst lengths: 1, 2, 4, 8 locations or full page. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the synchronous dram uses an intern al pipelined architecture to achieve high-speed operation. this architecture is compartible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to ac hieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hi de the precharge cycles and provide seamless, high-speed, randon-access operation. read and write accesses to the hynix synchronous dram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are us ed to select the bank and the starting column locati on for the burst access. all inputs are lvttl compatible. devices will have a v dd and v ddq supply of 3.3v (nominal).
rev 1.1 / dec. 2007 4 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series 256mb synchronous dram(16m x 16) features ? standard sdram protocol ? internal 4bank operation ? power supply voltage : v dd = 3.3v, v ddq = 3.3v ? all device pins are compatible with lvttl interface ? low voltage interface to reduce i/o power ? 8,192 refresh cycles / 64ms ? programmable cas latency of 2 or 3 ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? 0 o c ~ 70 o c operation ? package type : 54ball, 0.8mm pitch fbga (lead free, lead) hy5v56f(l)fp series : lead free hy5v56f(l)f series : leaded ordering information note: 1. hy5v56ff(p) series: normal power 2. hy5v56flf(p) series: low power 3. hy5v56f(l)f series: leaded 54pin tsopii 4. hy5v56f(l)fp series: lead free 54pin tsopii part number clock frequency cas latency power voltage organization interface 54pin fbga hy5v56f(l)f-6 166mhz 3 normal 3.3v 4banks x 4mbits x16 lvttl leaded hy5v56f(l)f-h 133mhz 3 hy5v56f(l)f-6 166mhz 3 low power hy5v56f(l)f-h 133mhz 3 hy5v56f(l)fp-6 166mhz 3 normal lead free hy5v56f(l)fp-h 133mhz 3 hy5v56f(l)fp-6 166mhz 3 low power hy5v56f(l)fp-h 133mhz 3
rev 1.1 / dec. 2007 5 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series ball configuration 54 ball fbga 0.8m m ball pitch < bottom view > 9 8 7 3 21 a b c d e f g h j 54 ball fbga 0.8m m ball pitch < bottom view > 9 8 7 3 21 a b c d e f g h j ) + # $ % " ( ' & 744 %2 %2 %2 %2 6%2. " " 744 %2 %2 %2 %2 /$ $-, " " " 7442 7%%2 7442 7%%2 744 $,& " " " 7%%2 7442 7%%2 7442 7%% $"4 #" " " %2 %2 %2 %2 -%2. 3"4 #" " " 7%% %2 %2 %2 %2 8& $4 " 7%% < top view >
rev 1.1 / dec. 2007 6 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series 54_ball fbga descriptions symbol type description clk input clock : the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke input clock enable: controls internal clock signal and when deacti vated, the sdram will be one of the states among power down, suspend or self refresh cs input chip select: enables or disables all inpu ts except clk, cke and dqm ba0, ba1 input bank address: selects bank to be activated during ras activity selects bank to be read/written during cas activity a0 ~ a12 input row address: ra0 ~ ra12, column address: ca0 ~ ca8 auto-precharge flag: a10 ras , cas , we input command inputs: ras , cas and we define the operation refer function truth table for details ldqm, udqm i/o data mask: controls output buffers in read mode and masks input data in write mode dq0 ~ dq15 i/o data input / output: multiplexed data input / output pin v dd / v ss supply power supply for internal circuits and input buffers v ddq / v ssq supply power supply for output buffers nc - no connection : these pads should be left unconnected
rev 1.1 / dec. 2007 7 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series functional block diagram 4mbit x 4banks x 16 i/o synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we ldqm, udqm a0 a1 ba1 ba0 a12 row pre decoder refresh dq0 dq15 x decorders x decoders x decorders x decorders y decoerders 4m x16 bank0 4m x16 bank1 4m x16 bank2 4m x16 bank3 memory cell array data out control burst length pipe line control
rev 1.1 / dec. 2007 8 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series absolute maximum rating dc operating condition note: 1. all voltages are referenced to v ss = 0v. 2. v ih( max) is acceptable vddq + 2v for a pulse width with <= 3ns of duration. 3. v il (min) is acceptable -2.0v for a pu lse width with <= 3ns of duration. ac operating test condition (t a = 0 to 70 o c , v dd =3.3 0.3v / v ss =0v) note: 1. see next page parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on vdd supply relative to v ss v dd , v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1w soldering temperature . time t solder 260 . 10 o c . sec parameter symbol min max unit note power supply voltage v dd , v ddq 3.0 3.6 v 1 input high voltage v ih 2.0 v ddq + 0.3 v 1, 2 input low voltage v il -0.3 0.8 v 1, 3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4 / 0.4 v input timing measurement reference level voltage v trip 0.5 x v ddq v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage v outref 0.5 x v ddq v output load capacitance for access time measurement cl 50 pf 1
rev 1.1 / dec. 2007 9 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series capacitance (f=1mhz) dc characterristics i (t a = 0 to 70 o c ) note: 1. vin = 0 to 3.6v, all other balls are not tested under vin =0v 2. dout is disabled, vout=0 to 3.6 parameter pin symbol min max unit input capacitance clk ci1 2.0 4.0 pf a0 ~ a12, ba0, ba1, cke, cs , ras , cas , we ci2 2.0 4.0 pf ldqm, udqm ci3 2.0 4.0 pf data input / output capacitance dq0 ~ dq15 ci/o 3.5 6.5 pf parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v ioh = -4ma output low voltage v ol - 0.4 v iol = +4ma z0 = 50 ohom 50pf rt = 50 ohom vtt = 1.4v output ac output load circuit 50pf rt = 50 ohom vtt = 1.4v output dc output load circuit
rev 1.1 / dec. 2007 10 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series dc characteristics ii (ta= 0 to 70 o c ) note: 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open. 2. min. of trc (refresh ras cycle time) is shown at ac characteristics ii 3. hy5v56flf(p) series: no rmal, hy5v56flf(p ) series: low power parameter symbol test condition speed unit note 6 h operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 100 90 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns normal 2.0 ma 3 low power 1.0 ma i dd2ps cke v il (max), t ck = normal 2.0 ma 3 low power 1.0 ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 15 ma i dd2ns cke v ih (min), t ck = input signals are stable. 8 active standby cur- rent in power down mode i dd3p cke v il (max), t ck = 15ns 3 ma i dd3ps cke v il (max), t ck = 3 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are changed one time during 2clks. all other pins v dd -0.2v or 0.2v 30 ma i dd3ns cke v ih (min), t ck = input signals are stable. 20 burst mode operating current i dd4 t ck t ck (min), i ol =0ma all banks active 100 90 ma 1 auto refresh current i dd5 t rc t rc (min), all banks active 180 170 ma 2 self refresh current i dd6 cke 0.2v normal 2.0 ma 3 low power 1.0
rev 1.1 / dec. 2007 11 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series ac characteristics i (ac operating conditions unless otherwise noted) note: 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with input signal s of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter symbol 6 h unit note min max min max system clock cycle time cl = 3 t ck3 6.0 1000 7.5 1000 ns cl = 2 t ck2 7.5 1000 10 1000 ns clock high pulse width t chw 2.5 - 2.5 - ns 1 clock low pulse width t clw 2.5 - 2.5 - ns 1 access time from clock cl = 3 t ac3 -5.4-5.4 ns 2 cl = 2 t ac2 -6-6 ns 2 data-out hold time t oh 2.0 - 2.5 - ns data-input setup time t ds 1.5 - 1.5 - ns 1 data-input hold time t dh 0.8 - 0.8 - ns 1 address setup time t as 1.5 - 1.5 - ns 1 address hold time t ah 0.8 - 0.8 - ns 1 cke setup time t cks 1.5 - 1.5 - ns 1 cke hold time t ckh 0.8 - 0.8 - ns 1 command setup time t cs 1.5 - 1.5 - ns 1 command hold time t ch 0.8 - 0.8 - ns 1 clk to data output in low-z time t olz 1.0 - 1.0 - ns clk to data output in high-z time cl = 3 t ohz3 2.7 5.4 2.7 5.4 ns cl = 2 t ohz2 2.7 5.4 3 6 ns
rev 1.1 / dec. 2007 12 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series ac characteristics ii (ac operating conditions unless otherwise noted) note: 1. a new command can be given t rc after self refresh exit. parameter symbol 6 h unit note min max min max ras cycle time operation t rc 60 - 63 - ns auto refresh t rrc 60 - 63 - ns ras to cas delay t rcd 18 - 20 - ns ras active time t ras 42 100k 42 100k ns ras precharge time t rp 18 - 20 - ns ras to ras bank active delay t rrd 12 - 15 - ns cas to cas delay t ccd 1-1-clk write command to data-in delay t wtl 0 - 0 - clk data-in to precharge command t dpl 2-2-clk data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-clk dqm to data-in mask t dqm 0-0-clk mrs to new command t mrd 2-2-clk precharge to data output high-z cl = 3 t proz3 3-3-clk cl = 2 t proz2 2-2-clk power down exit time t dpe 1-1-clk self refresh exit time t sre 1-1-clk1 refresh time t ref -64-64ms
rev 1.1 / dec. 2007 13 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series basic functional description mode register ba1ba0a12a11a10 a9 a8a7a6a5a4a3a2a1a0 0 0 0 0 0 op code 0 0 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0sequential 1interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 4 4 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 r e s e r v e d 0 0 1 r e s e r v e d 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 r e s e r v e d 1 1 0 r e s e r v e d 1 1 1 reserved
rev 1.1 / dec. 2007 14 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high. 2. see to next page (dqm truth table) function cken-1 cken cs ras cas we dqm addr a10 /ap ba note mode register set h x l l l l x op code no operation h x l h h h x x device deselect h x h x x x x x bank active h x l l h h x row address v read h x l h l h col- umn l v read with autoprecharge h x l h l h x col- umn h v write h x l h l l x col- umn l v write with autoprecharge h x l h l l x col- umn h v precharge all banks h x l l h l x x h x precharge selected bank h x l l h l x x l v burst stop h x l h h l x x dqm h x x v x 2 auto refresh h h l l l h x x burst-read single-write h x l l l h x a9 pin high (other pins op code) self refresh entry h l l l l h x x self refresh exit l h hx xx xx1 lhhh precharge power down entry hl hx xx xx lhhh precharge power down exit l h hx xx xx lhhh clock suspend entry h l hx xx xx lv vv clock suspend exit l h x x x
rev 1.1 / dec. 2007 15 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series dqm truth table note 1. h: high level, l: low level, x: don ' t care 2. write dqm latency is 0 clk and read dqm latency is 2 clk function cken-1 cken ldqm udqm data write/output enable h x l l data mask/output disable h x h h lower byte write/output enable, upper byte mask/output disable hxlh lower byte mask/output disable, upper byte write/output enable hxhl
rev 1.1 / dec. 2007 16 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series current state truth table (sheet 1 of 4) current state command action notes cs ras cas we ba0/ ba1 a max -a0 description idle l l l l op code mode register set set the mode register l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba row add. bank activate activate the specified bank and row lh l l ba col add. a10 write/writeap illegal 4 lh l h ba col add. a10 read/readap illegal 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation or power down 3 row active l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap start write : optional ap(a10=h) 6 lh l h ba col add. a10 read/readap start read : optional ap(a10=h) 6 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 llhl ba x precharge termination burst: start the precharge l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8,9 lh l h ba col add. a10 read/readap termination burst: start read(optional ap) 8 l h h h x x no operation continue the burst
rev 1.1 / dec. 2007 17 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series current state truth table (sheet 2 of 4) current state command action notes cs ras cas we ba0/ ba1 a max -a0 description read h x x x x x device deselect continue the burst write l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 llh l ba x precharge termination burst: start the precharge 10 l l h h ba row add. bank activate illegal 4 lh l l ba col add. a10 write/writeap termination burst: start write(optional ap) 8 lh l h ba col add. a10 read/readap termination burst: start read(optional ap) 8,9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst read with auto precharge l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 12 l h l h ba col add. a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst
rev 1.1 / dec. 2007 18 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series current state truth table (sheet 3 of 4) current state command action notes cs ras cas we ba0/ ba1 a max -a0 description precharging l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 llh l ba x precharge no operation: bank(s) idle after t rp l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 lhh h x x no operation no operation: bank(s) idle after t rp h x x x x x device deselect no operation: bank(s) idle after t rp row activating l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,11,1 2 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,12 lhh h x x no operation no operation: row active after t rcd h x x x x x device deselect no operation: row active after t rcd write recovering l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap start write: optional ap(a10=h) l h l h ba col add. a10 read/readap start read: optional ap(a10=h) 9 lhh h x x no operation no operation: row active after t dpl
rev 1.1 / dec. 2007 19 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series current state truth table (sheet 4 of 4) current state command action notes cs ras cas we ba0/ ba1 a max -a0 description write recovering h x x x x x device deselect no operation: row active after t dpl write recovering with auto precharge l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add. a10 write/writeap illegal 4,12 l h l h ba col add. a10 read/readap illegal 4,9,12 lhh h x x no operation no operation: precharge after t dpl h x x x x x device deselect no operation: precharge after t dpl refreshing l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 lhh h x x no operation no operation: idle after t rc h x x x x x device deselect no operation: idle after t rc mode register accessing l l l l op code mode register set illegal 13 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add. a10 write/writeap illegal 13 l h l h ba col add. a10 read/readap illegal 13 lhh h x x no operation no operation: idle after 2 clock cycles h x x x x x device deselect no operation: idle after 2 clock cycles
rev 1.1 / dec. 2007 20 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series note : 1. h: logic high, l: logic low, x: don ' t care, ba: bank address, ap: auto precharge. 2. all entries assume that cke was ac tive during the preceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function may be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if t rcd is not satisfied. 7. illegal if t ras is not satisfied. 8. must satisfy burst interrupt condition. 9. must satisfy bus contention, bus turn aro und, and/or write re covery requirements. 10. must mask preceding data which don ' t satisfy t dpl . 11. illegal if t rrd is not satisfied 12. illegal for single bank, but legal for other banks in multi-bank devices. 13. illegal for all banks.
rev 1.1 / dec. 2007 21 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series cke enable(cke) truth table (sheet 2 of 1) current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 addr self refresh h x xx xxx x invalid 1 lhhxxxxx exit self refresh with device deselect 2 lhlhhhxx exit self refresh with no operation 2 lhlhhlxx illegal 2 lhlhlxxx illegal 2 lhllxxxx illegal 2 l l xx xxx x maintain self refresh power down h x xx xxx x invalid 1 lh hx xxx x power down mode exit, all banks idle 2 lhhhx x lhl lxxx x illegal 2 xlxx x xxlx x l l xx xxx x maintain power down mode all banks idle hhhxxx refer to the idle state section of the current state truth table 3 hhlhxx 3 hhllhx 3 hhlllhxx auto refresh h h l l l l op code mode register set 4 hlhxxx refer to the idle state section of the current state truth table 3 hllhxx 3 hlllhx 3 hllllhxx entry self refresh 4 h l l l l l op code mode register set l x xx xxx x power down 4
rev 1.1 / dec. 2007 22 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series cke enable(cke) truth table (sheet 2 of 2) note : 1. for the given current state cke must be low in the previous cycle. 2. when cke has a low to high transition, the clock and other inputs are re-enabled asynchro nously. when exiting power down mod e, a nop (or device deselect) comman d is required on the first positive edge of clock after cke goes high. 3. the address inputs depend on the command that is issued. 4. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idle state. 5. when cke has a low to high t ransition, the clock and other inputs are re-ena bled asynchronously. when exiting deep power down mode , a nop (or device deselect) command is re quired on the first positive edge of clock after cke goes high and is maintained for a minimum 200usec. current state cke command action notes previous cycle current cycle cs ras cas we ba0, ba1 addr any state other than listed above h h xx xxx x refer to operations of the current state truth table h l xx xxx x begin clock suspend next cycle l h xx xxx x exit clock suspend next cycle l l xx xxx x maintain clock suspend
rev 1.1 / dec. 2007 23 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series mobile sdr sdram operation state diagram idle power down row active act write read active power down write with ap read with ap write read read suspend reada suspend write suspend writea suspend read write wri te a r ea da precharge all automatic sequence manual input ck e h ig h c ke low cke lo w cke hi g h ck e high c k e lo w c k e l o w c k e h i g h c k e lo w c k e h igh self refresh mode register set auto refresh precharge all bank power on r e f a refs refx mrs pre p r e p r e cke l o w c ke h i g h act : active mrs : mode regi ster set pre : precharge preall : precharge all banks refa : auto refresh refs : enter self refresh refsx : exit self refresh read : read w/o auto precharge reada : read with auto precharge wri te : wr i t e w/ o aut o precharge wri tea : write with auto precharge
rev 1.1 / dec. 2007 24 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series deselect the deselect function (cs = high) prevents new commands from being executed by the sdram, the sdram ignore command input at the clock. however, the internal status is held. the synchronous dram is effectively deselected. operations already in progress are not affected. no operation the no operation (nop) command is used to perform a nop to a sdram that is selected (cs = low, ras = cas = we = high). this command is not an execution command. however, the internal operations continue. this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. (see to next figure) active the active command is used to activate a row in particular bank for a subsequent read or write access. the value of the ba0,ba1 inputs selects the bank, and the address provided on a0-a12(or the highest address bit) selects the row. this row remains active (or open) for accesses until a precha rge command is issued to th at bank. (see to next fig- ure) cs a0~a9, a11, a12 we cas ras don't care clk cke high-z ba0,1 cs a0~a9, a11, a12 we bank address cas ras row address don't care clk cke high-z ra ba ba0,1 nop command activating a specific row in a specific bank
rev 1.1 / dec. 2007 25 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read / write command before executing a read or write operation, the correspo nding bank and the row address must be activated by the bank active (act) command. an interval of trcd is required between the bank active command input and the follow- ing read/write command input. the read command is used to initiate a burst read to an active row. the value of ba0 and ba1 selects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto precharg e is used. if auto-precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent access. the valid data-out elements will be available cas latency after the read command is issued. the write command is used to initiate a burst write access to an active row. the value of ba0, ba1 selects the bank and address inputs select the starting column location. the value of a10 determines whether or not auto precharg e is used. if auto-precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent access. read / write command cs a0 ~ a8 we cas ras don't care clk cke high-z ca ba ba0,1 enable auto precharge disable auto precharge read command operation write command operation a10 cs a0 ~ a8 we cas ras /clk clk cke high-z ca ba ba0,1 a10
rev 1.1 / dec. 2007 26 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read a read operation starts when a read command is input. output buffer becomes low-z in the (/cas latency - 1) cycle after read command set. the sdra m can perform a burst read operation. the burst length can be set to 1, 2, 4 and 8. the start address for a burst read is specified by the column address and the bank select address at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the /cas latency. the /cas latency can be set to 2 or 3. when the burst length is 1, 2, 4 and 8 the dout buffer au tomatically becomes high-z at the next clock after the suc- cessive burst-length data has been output. the /cas latency and burst length must be specified at the mode register. read burst showing cas latency clk tck command dq undefined rea d nop nop do0 do1 do2 do3 toh tlz tac cl = 2 rea d nop nop nop do0 do1 do2 do3 toh tlz tac cl = 3 command dq don't care
rev 1.1 / dec. 2007 27 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read burst showing bl clk tc k cmd dq re ad n op n op do 0 toh tlz cl = 2 do 0 do 1 do 0 do 1 do 2 do 3 do 0 do 1 do 2 do 3 do 4 do 5 do 6 do 7 dq dq dq bl=1 bl=2 bl4 bl=8 undefined don't care
rev 1.1 / dec. 2007 28 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read to read data from a read burst may be concat enated or truncated by a subsequent read command. the first data from the new burst follows either the last elemen t of a completed burst or the last desi red element of a longer burst that is being truncated. when another read command is executed at the same ro w address of the same bank as the preceding read com- mand execution, the second read can be performed after an in terval of no less than 1 clock. even when the first com- mand is a burst read that is not yet finished, th e data read by the second command will be valid. consecutive read bursts a read command can be initiated on any clock cycle follow ing a previous read command. non-consecutive reads are shown in figure. full-speed random read accesses within a page or pages can be performed as shown in fig. clk do a0 read cl =3 cl =2 don't care command address dq dq do a1 do b0 do b1 do a0 do a1 do b0 read s ba, col b ba, col a nop nop
rev 1.1 / dec. 2007 29 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series non-consective read bursts randum read bursts clk do n do n read read ba, col n cl =3 cl =2 don't care 1) do n (or b ): data out from column n 2) ba, col n (b) = bank a, column n (b) 3) burst length = 4 : 3 subseqnent elements of da ta out appear in the prog rammed order following do n (b) command address dq dq ba, col b do b do b do g clk cl =3 cl =2 don't care dq dq read read read read command ba, col n address ba, col b ba, col x ba, col g do n do b do n' do x do x' do b' do g do g' do x' do n do n' do x do b do b' do g s 1) do n, etc: data out from column n, etc n', x', etc : data out elements, accoding to the programmd burst order 2) ba, col n = bank a, column n 3) burst length = 1, 2, 4, 8 or full page in cases shown 4) read are to active row in any banks
rev 1.1 / dec. 2007 30 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read burst terminate data from any read burst may be truncated with a bu rst terminate command. the burst terminate latency is equal to the read (cas) latency, i.e. , the burst terminate command should be issued x cycles after the read com- mand where x equals the desired data-out element. terminating a read burst clk cl =3 cl =2 don't care dq dq read burst command ba, col n address do n do n' do n do n' 1) do n : data out from column n 2) ba, col n = bank a, column n 3) cases shown are bursts of 4, 8, or full page terminated after 2 data elements
rev 1.1 / dec. 2007 31 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read to write data from read burst must be completed or truncated before a subsequent write command can be issued. if trun- cation is necessary, the burst terminate comm and must be used, as shown in next fig. read to write note : 1. same bank, same row address: when the write command is exec uted at the same row address of the same bank as the preced- ing read command, the write command can be pe rformed after an interval of no less than 1 clock. however, dqm must be set high so that the output buffer beco mes high-z befo re data input. 2. same bank, different row address: when the row address chan ges, consecutive write commands cannot be executed; it is nec- essary to separate the two co mmands with a precharge command and a bank active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 cycle, provide d that the other bank is in the bank active state. however, dqm mu st be set high so that the outp ut buffer becomes high-z before data input. clk cl =3 cl =2 don't care dq dq read burst write command ba, col n address do n do n' do n do n' ba, col b d i b0 d i b1 d i b2 di b3 d i b0 d i b1 d i b2 di b3 1) do n = data out from column n; di b = data in to column b
rev 1.1 / dec. 2007 32 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series read to precharge following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. note that part of the row precharge time is hidd en during the access of the last data element(s). in the case of a fixed-length burst being executed to co mpletion, a precharge command issued at the optimum time (as described above) provides the same operation that woul d result from the same fixed- length burst with auto pre- charge. the disadvantage of the prechargecommand is that it requires that the comm and and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to trun- cate fixed-length or full-page bursts. read to precharge clk cl =3 cl =2 don't care dq dq read pre act command ba, col n address bank a, all ba, row do n trp do n 1) do n = data out from column n 2) note that precharge may not be issued before tr as ns after the active command for applicable banks. 3) the active command may be applied if trc has been met.
rev 1.1 / dec. 2007 33 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series write input data appearing on the da ta bus, is written to the memory array su bject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the correspond ing data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a wr ite will not be executed to that byte / column location. during write bursts, the first valild data-in element will be registered coincident with the write command. subse- quent data elements will be registered on each successiv e positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dq will remain high-z and any additional input data will be ignored. a full-page burst will continue until terminated. data for any write burst may be truncated with a subseq uent write command, and data for a fixed-length write burst may be immediately followed by data for a write command. the new write comm and can be issued on any clock following the previous write command, and the data pr ovided coincident with the new command applies to the new command. basic write timing parameters for write burst operation note : 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writ es, the second write command has priority. 2. same bank, different row address: when the row address chan ges, consecutive write commands cannot be executed; it is nec- essary to separate the two write commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. in the case of burst write, the second write command has priority. clk don't care dq write command ba, col b address d i b0 dq d i b0 d i b1 dq d i b0 d i b1 d i b2 d i b3 dq d i b0 d i b1 d i b2 d i b3 d i b4 d i b6 d i b7 cl = 2 or 3 bl = 1 bl = 2 bl = 4 bl = 8 d i b5
rev 1.1 / dec. 2007 34 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series write to write data for any write burst may be concatenated with or tr uncated with a subsequent write command. in either case, a continuous flow of input data, can be maintained. the new write command can be issued on any positive edge of the clock following the previous write command. the first data-in element from the new burst is applied after either the last element of a complete d burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after th e first write command, where x equals the number of desired data-in element. concatenated write bursts random write cycles clk don't care write write command ba, col b address dq d i b0 d i b1 d i b2 d i b3 d i n0 d i n2 d i n3 cl = 2 or 3 d i n1 ba, col n dm clk don't care write write write write write nop command ba, col b address dq d i b d i b' d i x d i x s d i n d i a cl = 2 or 3 d i n s ba, col n ba, col x ba, col a ba, col g d i a s d i g d i g s dm
rev 1.1 / dec. 2007 35 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series write to read the preceding burst write operation can be aborted and a ne w burst read operation can be started by inputting a new read command in the write cycle. the data of the read command (read) is output after the lapse of the /cas latency. the preceding write operation (writ) writes on ly the data input before the read command. the data bus must go into a high-i mpedance state at least one cycle be fore output of the latest data. note: 1. same bank, same row address: when the read command is exec uted at the same row address of the same bank as the preced- ing write command, the read command can be perf ormed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed. 2. same bank, different row address: when the row address chan ges, consecutive read commands cannot be executed; it is nec- essary to separate the two co mmands with a precharge command and a bank active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address). clk don't care dq write read command ba, col b address dq d i b0 d i b1 d o n0 d o n2 d o n3 bl = 4 d o n1 d i b0 d i b1 bl = 4 cl = 3 ba, col n cl = 2 d o n0 d o n2 d o n3 d o n1
rev 1.1 / dec. 2007 36 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series write to precharge data for any write burst may be followed by a subseque nt precharge command to the same bank (provided auto precharge was not activated). when th e precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two comman ds is 1 clock. however, if the burst write operation is unfinished, the input data must be mask ed by means of dqm for assurance of th e clock defined by tdpl. to follow a write without truncating the write burst, tdpl should be met as shown in fig. non-interrupting write to precharge data for any write burst may be truncated by a su bsequent precharge command as shown in figure. note that only data-inthat are registered prior to the t dpl period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in next fig. following the precharge command, a subsequent com- mand to the same bank cannot be issued until trp is met. interrupting write to precharge clk write pre command ba, col b address dq d i b0 d io b2 bl = 4 d i b1 cl = 2 or 3 tdpl d i b3 clk dq write pre command ba, col b address d i b0 d io b2 bl = 4 d i b1 cl = 2 or 3 tdpl
rev 1.1 / dec. 2007 37 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series burst terminate the burst terminate command is used to truncate read bu rsts (with autoprecharge disabled). the most recently registered read command prior to the burst terminate comma nd will be truncated, as shown in the operation sec- tion of this datasheet. note the burs t terminate command is not bank specific. this command should not be used to terminate write bursts. burst terminate command cs a0 ~ a9 a11, a12 we cas ras don't care clk cke high-z ba0, 1
rev 1.1 / dec. 2007 38 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series precharge the precharge command is used to deactivate the open ro w in a particular bank or the open row in all banks. another command to the same bank (or banks) being prec harged must not be issued until the precharge time (t rp ) is completed. if one bank is to be precharged, the particular bank addres s needs to be specified. if all banks are to be precharged, a10 should be set high along with the precharge command . if a10 is high, ba0 and ba1 are ignored. a precharge command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. precharge command auto precharge auto precharge is a feature which performs the same individu al bank precharge function as described above, but with- out requiring an ex plicit command. this is accomplished by using a10 (a10=h igh), to enable auto precharge in conjunction with a specific read or write command. this precharges the bank/row afte r the read or write burst is complete. auto precharge is non persistent, so it should be enabled with a read or write command each time auto precharge is desired. auto precharge ensures that a precharge is in itiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharge time (t rp ) is completed. don't care cs a0~a9 a11, a12 we cas ras cke high-z ba ba0,1 a10 bank address a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto- precharge function is enabled. while a10 = low, auto- precharge function is disabled.
rev 1.1 / dec. 2007 39 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series auto refresh and self refresh hynix sdr sdram devices require a refresh of all rows in any rolling 64ms interval. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode: auto refresh. this command is used during normal oper ation of the hynix sdr sdram. it is no n persistent, so must be issued each time a refresh is required. the refresh addressing is genera ted by the internal refresh co ntroller.the hynix sdr sdram requires auto refresh commands at an average periodic interval of t ref . to allow for improved efficiency in scheduling and switchin g between tasks, some flexibil ity in the absolute refresh interval is provided. a maximum of eight auto refresh commands can be posted to an y given sdr sdram, and the maximum absolute interval between any auto refresh command and the next auto refresh command is 8*t ref . -self refresh. the self refresh command is initiated lik e an auto refresh command except cke is disabled(low). this state retains data in the sdr sdram, even if the rest of the system is powered down. note refresh interval timing while in self refresh mode is scheduled intern ally in the sdr sdram and may vary and may not meet tref time. after executing a self-refresh command, the self-refresh operation continues while cke is held low. during selfrefresh operation, all row addresses are refreshed by the internal refr esh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refresh a ddresses in or within tref (max.) period on the condition 1 and 2 below. 1. enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode. note: tref (max.) / refresh cycles. the use of self refresh mode introduces the possibility th at an internally timed event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recom- mended. the self refresh command is used to retain cell data in the sdr sdram. in the se lf refresh mode, the sdr sdram operates refresh cycle asynchronously.
rev 1.1 / dec. 2007 40 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series auto refresh command self refresh entry command note 1: if all banks are in the idle status and cke is inactive (low level), the self refresh mode is set. function cken-1 cken cs ras cas we dqm addr a10/ap ba auto refresh h h l l l h x x self refresh entry h l l l l h x x cs a0 ~ a9 a11, 12 we cas ras don't care clk cke ba0, 1 low-z cs a0 ~ a9 a11, 12 we cas ras don't care clk cke high-z ba0, 1
rev 1.1 / dec. 2007 41 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series mode register set the mode registers are loaded via the address bits. ba0 and ba1 are used to select the mode register. see the mode register descriptio n in the register definition section. the mode register set command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until t mrd is met. mode register set command note: ba0=ba1=low loads the mode register. code = mode register / extend ed mode register selection (ba0, ba1) and op-code (a0 - an) t mrd definition cs a0 ~ a9 a11, a12 we cas ras don't care clk cke ba0, 1 code code high-z mrs nop valid code valid tmrd clk command address don't care
rev 1.1 / dec. 2007 42 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series power down power down occurs if cke is set low co incident with device deselect or no p command and when no accesses are in progress. if power down occurs when all ba nks are idle, it is precharge power down. if power down occurs when one or more banks are active, it is referred to as active power down. the device cannot stay in this mode for longer than the refresh requirements of the device, withou t losing data. the power down state is exited by setting cke high while issu ing a device deselect or nop command. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active po wer-down. entering power-down deactivates the input and output buffers, excluding cke, for maximum power sa vings while in standby. power-down command note: this case shows cke low coincident with no operation. alternately power down entry can be achieved with cke low coincident with device deselect. clk cke command nop nop active input buffers gated off trcd tras trc enter power-down mode. exit power-down mode. all banks idle don s t care cs a0 ~ a9 a11, 12 we cas ras don't care clk cke ba0, 1 cke_low
rev 1.1 / dec. 2007 43 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series power up and initialization like a synchronous dram, low power sdram(mobile sdram) mu st be powered up and initialized in a predefined man- ner. power must be applied to v dd and v ddq (simultaneously). the clock signal must be started at the same time. after power up, an initial pause of 200 usec is required. and a precharge all command will be issued to the mobile sdram. then, 8 or more auto refresh cycles will be prov ided. after the auto refresh cycles are completed, a mode register set(mrs) command will be issued to program the specific mode of oper ation (cas latency, burst length, etc.) and a extended mode register set command will be issued to program specific mode of self refresh operation(pasr). the following these cycles, the mobile sdram is ready for normal opeartion. programming the registers mode register the mode register contains the specific mode of operation of the sdr sdram. this register includes the selection of a burst length(1, 2, 4, 8, full page), a cas latency(1, 2 or 3), a burst type. the mode register set must be done before any activate command after the power up sequence. any contents of the mode register be altered by re-programming the mode register through the execution of mode register set command. bank(row) active the bank active command is used to ac tivate a row in a specified bank of th e device. this command is initiated by activating cs , ras and deasserting cas , we at the positive edge of the clock. the value on the ba1 and ba0 selects the bank, and the value on the a0-a12 selects the row. this row remain s active for column access until a precharge command is issued to that bank. read and write opeartions can only be initiated on this activated bank after the min- imum t rcd time is passed from the activate command. read the read command is used to initia te the burst read of data. this co mmand is initiated by activating cs , cas , and deasserting we , ras at the positive edge of the clock. ba1 and ba 0 inputs select the bank, a8-a0 address inputs select the sarting column location. the value on input a10 determines whether or not auto precharge is used. if auto pre- charge is selected the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain acti ve for subsequent accesses. the length of burst and the cas latency will be determined by the values programmed during the mrs command. write the write command is used to initia te the burst write of data. this co mmand is initiated by activating cs , cas , we and deasserting ras at the positive edge of the clock. ba1 and ba0 inputs select the bank, a8-a0 address inputs select the starting column location. the va lue on input a10 determines whether or not auto precharge is used. if auto precharge is selected the row be ing accessed will be precharged at the end of the write burst; if auto pre- charge is not selected, the row will re main active for subsequent accesses.
rev 1.1 / dec. 2007 44 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series precharge the precharge command is used to close the open row in a particular bank or the open row in all banks. when the precharge command is issued with address a10, high, then a ll banks will be precharged, and if a10 is low, the open row in a particular bank will be precharged. the bank(s) will be ava ilable when the minimum t rp time is met after the precharge command is issued. auto precharge the auto precharge command is issued to close the open ro w in a particular bank after read or write operation. if a10 is high when a read or write command is issued, the read or write with auto precharge is initiated. burst termination the burst termination is used to terminate the burst operat ion. this function can be a ccomplished by asserting a burst stop command or a precharge command during a burst read or write operation. the precharge command interrupts a burst cycle and close the active bank, and the burst stop command terminates the existing burst operation leave the bank open. data mask the data mask comamnd is used to mask read or write data. during a re ad operation, when this command is issued, data outputs are disabled and become high impedance after two clock delay. during a write operation, when this command is issued, data inputs ca n't be written with no clock delay. if data mask is initiated by asse rting low on dqm during the read cy cle, the data outputs are enabled. if dqm is asserted to high. the data outputs are masked (disabled) and become hi-z state after 2 cycle later. during the write cycle, dqm mask da ta input with zero latency dm cmd ck d0 d1 dq data masking 0 latency hi- z d in0 d0 d1 d0 d1 d in2 d0 d1 writ mk mk data masking 0 latency write data masking dm cmd ck d0 d1 dq data masking 2 latency hi- z d out0 d0 d1 d out1 d0 d1 d dot2 d0 d1 read mk read data masking
rev 1.1 / dec. 2007 45 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series clock suspend the clock suspend command is used to suspend the internal clock of sdr sd ram. the clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the operation of the device. during normal access mode, cke is keeping high. when cke is low, it freezes the internal clock and extends data read and write operations. (see examples in next figures) clk cke q1 q2 q3 q4 rd internal clk clock suspend mode wr d1 d2 d3 d4 clock suspend mode dq command cke command internal clk dq frozen int. clk by cke (cke = fixed low) masked by cke masked by cke frozen int. clk by cke (cke = fixed low)
rev 1.1 / dec. 2007 46 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series power down the power down command is used to re duce standby current. before this command is issued, all banks must be pre- charged and trp must be passed after a precharge command. once the power down comman d is initiated by keeping cke low, all of the input buff er except cke are gated off. auto refresh the auto refresh command is used during normal operation and is similar to c br refresh in coventional drams. this command must be issued each time a refresh is requir ed. when an auto refresh command is issued , the address bits is ''don't care'', because the specific address bi ts is generated by internal refresh address counter. self refresh the self refresh command is used to re tain cell data in sdram. in the self refresh mode, the sdram operates refresh cycle asynchronously. the self refresh command is initiated like an auto refresh command except cke is disa- bled(low).
rev 1.1 / dec. 2007 47 111 synchronous dram memory 256mbit hy5v56f(l)f(p) series package information 54 ball fbga 0.8mm pitch (size 8.0mm x 10.0mm) unit [mm] 0.80 bottom view 0.34 +/- 0.05 0.80 typ. 0.40 0.80 typ. 1.10 max 3.20 1.60 0.45 +/- 0.05 a1 index mark 1.375 10.0 typ. 1.80 8.00 typ.

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